One type of prior non-volatile semiconductor memory is the flash electrically-erasable programmable read-only memory ("flash EEPROM"). The flash EEPROM can be programmed by a user, and once programmed, the flash EEPROM retains its data until erased. For certain prior flash EEPROMs, electrical erasure erases the entire memory array of the device. The flash EEPROM may then be programmed with new code.
One prior flash memory technology is the ETOX.TM. II technology of Intel Corporation of Santa Clara, Calif. FIG. 1 shows a prior ETOX.TM. II flash memory cell 10 of Intel Corporation. Prior flash memory cell 10 has a select gate 12, a floating gate 14, a source 16, and a drain 18. Source 16 and drain 18 reside within substrate 19. Substrate 19 is grounded. Flash memory cell 10 is comprised of a single transistor. Floating gate 14 is used for charge storage.
The field effect transistor ("FET") of flash memory cell 10 is turned on and off by the absence or presence of charge on floating gate 14 sitting above the conducting channel. Once excess electrons are placed on floating gate 14, the electrons are trapped there by the surrounding nonconducting oxide. The electric field the excess electrons produce will turn off the FET of memory cell 10, storing a logic 0 for the bit location represented by memory cell 10. When, however, no excess electrons are trapped on floating gate 14, the FET channel of memory cell 10 can conduct current and the cell 10 has a logic value of 1.
FIG. 1 shows a typical configuration of prior flash memory cell 10 for programming. A prior Quick-Pulse Programming.TM. algorithm of Intel Corporation is a type of prior algorithm that can be used as a microprocessor to program the flash memory. The programming mechanism for prior ETOX.TM. II flash memory cell 10 is hot electron injection. For programming, the drain 18 voltage V.sub.D is set to on the order of 6.5 volts and the gate 12 voltage V.sub.G is set to on the order of 12 volts. The source 16 of cell 10 is grounded.
The relatively high drain 18 program voltage on the order of 6.5 volts generates "hot" electrons that are swept across the channel of cell 10. These hot electrons collide with other atoms along the way, creating even more free electrons. Meanwhile, the relatively high voltage of approximately 12 volts on control gate 12 of cell 10 attracts these free electrons across the lower gate oxide into the floating gate 14, where those electrons are trapped. This programming process typically takes on the order of ten microseconds.
In the prior art, the program voltage is then disabled. The read circuits of the flash memory are enabled. For a prior art flash memory of Intel Corporation, there is then a delay of approximately six microseconds before a verify operation is performed.
This verify operation is a read operation with respect to the memory cells of the byte that has been programmed. For a verify operation, there should be on the order of one volt on drain 18, 7.2 volts on gate 12, and ground on source 16.
The six microsecond delay between the enablement of the read circuits and an actual verify operation allows time for drain 18 voltage V.sub.D to discharge from on the order of 6.5 volts (the programming voltage) to approximately 1.0 volts (the drain read voltage). The actual discharge time is a time that varies from device to device. The prior six microsecond delay was chosen to allow for variations from memory to memory in actual discharge times.
Once the six microsecond delay elapses, the addressed byte is read as part of the verify operation. Should the addressed byte require more time to reach the programmed state, the programming and verification operations are repeated until the byte is programmed.
Thus, the prior programming and verification operations for a prior Intel Corporation flash memory take at a minimum approximately 16 microseconds to complete--that is, 10 microseconds for programming plus a 6 microsecond delay before verification. Moreover, repetition of the programming and verification operations increases the amount of time required in multiples of 16 microseconds.
One disadvantage of the programming of that prior Intel flash memory is that the six microsecond delay before program verification slows down programming of the flash memory. If 128 Kilobits of the flash memory are being programmed, and if there is a six microsecond delay for each bit, then the total delay for programming the flash memory is approximately 0.786 seconds. Moreover, the six microsecond delay is a relatively conservative number that was chosen so as to cover variations in actual discharge time from memory to memory.
Quick-Erase.TM. algorithm of Intel Corporation is a type of prior algorithm that can be used by the microprocessor to erase the flash memory. The prior Quick-Erase.TM. algorithm requires that all bits of the memory first be programmed to their charged state, which is equivalent to data of 00 (hexidecimal). Erasure then proceeds by pulling the source of each transistor in the array up to a high voltage level for a period of 10 milliseconds, while keeping the transistor gates at zero volts. After each erase operation, verification is performed a byte at a time. For each byte during verification, the Quick-Erase.TM. algorithm allows up to approximately 3,000 full-array erase operations to be repeated before the algorithm generates an erase error signal. In other words, during verification, the algorithm steps through each byte at a time, repeating erasure if the byte has not yet been erased.
FIG. 2 shows a typical configuration of prior flash memory cell 10 for erasure. The erasure mechanism for prior ETOX.TM. II flash memory cell 10 is Fowler-Nordheim tunneling. For erasure, the gate 12 is grounded, the source 16 voltage Vs is set to 12 volts, and the drain 18 is left disconnected and, hence, floating. Typically the floating drain 18 charges up to an uncharacterized level.
During erasure, a high electric field is thus created between source 16 (at 12 volts) and floating gate 14 (at ground). This high electric field pulls electrons off floating gate 14. The erasure operation typically takes approximately 10 milliseconds.
In the prior art, the erasure voltage of 12 volts on the source is then disabled. The read circuits of the flash memory are enabled. For a prior art flash memory of Intel Corporation, there is then a delay of approximately six microseconds before a verify operation is performed with respect to a byte. For the verify operation, there should be on the order of one volt on drain 18, 3 volts on gate 12, and ground on source 16.
The six microsecond delay allows time for the floating drain 18 to discharge from its floating voltage (typically 3 to 6 volts) to the 1.0 volt drain 18 read voltage.
Once the 6 microsecond delay elapses, one byte of memory cells is read as part of the verify operation. If the addressed byte has not yet been erased, then erasure and verification operations are repeated until the algorithm determines that either the byte has been erased or enough erase cycles are performed to generate an erase error condition. The algorithm then steps to the next byte and performs a similar verification operation with respect to that byte. The algorithm eventually steps through all the bytes to be erased.
Thus, certain prior erasure and verification operations require a 6 microsecond delay for each iteration of the verification operation for each byte being erased up to approximately 3,000 iterations per byte are possible for the prior Quick-Erase.TM. algorithm.
One disadvantage of the erasure of the prior Intel flash memory is that the six microsecond delay per erasure verification iteration per byte shows down the erasure of the flash memory. Moreover, the six microsecond delay is a relatively conservative delay that was chosen to cover variations in actual discharge time that from memory to memory.